1. Field of the Invention
The present invention relates to semiconductor storage devices, such as a dynamic random access memory (DRAM) and the like.
2. Description of the Related Art
In recent years, higher-speed performance is highly required for semiconductor storage devices, particularly embedded memories used in system LSIs. To achieve this, there is a known technique in which a replica circuit is used to logically determine timing with which data on a bit line read from a memory cell is amplified by a sense amplifier. This technique enables optimization of a timing margin and can also reduce influence of external conditions, process variations or the like.
FIG. 15 shows a circuit configuration of a conventional DRAM including a replica circuit. The device comprises memory cells MC each including a transistor and a capacitor, word lines WL0 and WL1, bit line pairs BL0 to BLn/XBL0 to XBLn, sense amplifiers SA0 to SAn for amplifying data on the bit line pairs BL0 to BLn/XBL0 to XBLn, a dummy memory cell DMC, a dummy word line DWL, a dummy bit line pair DBL/XDBL, a data detecting circuit 201 for detecting data on the dummy bit line pair DBL/XDBL to output a signal, and an SA control generating circuit 202 for activating the sense amplifiers SA0 to SAn (see, for example, Japanese Unexamined Patent Application Publication No. H06-176568).
A core operation of the thus-configured conventional semiconductor storage device will be described with reference to a timing chart of FIG. 16. Initially, when an access request is input to the DRAM, a selected word line WL0 is activated, so that electric charges are transferred from the memory cells to the bit lines BL0 to BLn. At the same time, the dummy word line DWL is also activated, so that electric charges are similarly transferred to the dummy bit line DBL. This operation of transferring electric charges allows a change in potential level of the dummy bit line DBL to exceed a threshold of the data detecting circuit 201, thereby activating the SA control generating circuit 202, which in turn generates an SA control signal SEN. This signal activates the sense amplifier SA, which in turn amplifies the bit line pair BL/XBL to a desired potential.
Thus, by using a dummy memory cell to logically determining the time course (timing) of an operation for amplification of bit line data, an erroneous circuit operation can be eliminated, and the timing can be optimized, resulting in a faster operation.